The need to use low dielectric constant (low-k) interlayer dielectric (ILD) materials in scaled semiconductor devices is becoming necessary to reduce line-to-line capacitive coupling effects. However, the integration of these ILD materials is not necessarily a simple matter. One place this is evident is at the wafer saw/singulation process.
More specifically, because low-k dielectric materials are mechanically weaker than conventional silicon dioxide, they are more prone to saw-related scribe line damage, such as cracks. To the extent that this damage propagates to other areas of the wafer, semiconductor device yields and reliability can be compromised. This problem has been addressed by some manufacturers by first using a laser to scribe through the material formed over the wafer and then using a saw to cut through the bulk of the semiconductor wafer, thereby singulating it with a two-step process.
Lasers, however, are not without process integration issues. For example, as the laser scribes the wafer, it can produce a cloud of debris, and particles from the debris can deposit onto the wafer surface. If these particles deposit onto controlled collapse chip connection (C-4) bumps or other conductive structures, they can impact interconnectivity between the semiconductor device and its package.
This problem can be addressed by forming a wafer coat layer over the bumps to protect them during laser scribing so deposited particles can be rinsed off later during the wafer coat layer's removal. However, while wafer coat layers can be beneficial in this respect, they can also present integration issues. For example, both non-conformality and thickness variations of the wafer coat layer can impact the laser's ability to scribe the wafer.
Non-conformality manifests as a difference in the thickness of the wafer coat layer over the bumps and regions between the bumps. For example, it is not uncommon for a wafer coat layer to have a thickness of 1-2 microns over the bumps and a 40-50 micron thickness between the bumps. Thickness variations can be attributable to, among other things, poor wafer coat layer deposition uniformity; the relative proximity and spatial variation of wafer bumps or test structures; and/or small scale de-wetting and localized collection/pooling of the wafer coat layer as it adheres to structures having different compositions (e.g., surface tensions effects associated with the wafer bumps, passivation layer and/or recesses in the scribe street area).
Because ultimately it is the bumps that require protecting, adequate bump coverage is often only achieved by depositing thick wafer coat layers over areas of the substrate that need to be scribed (i.e. regions between the bumps). Thick wafer coat layers can lead to problems such as laser beam focusing lens contamination, run rate reduction, and scribe line defects due to incomplete and/or inadequate laser scribing. So, while wafer coat layers can be instrumental in preventing debris contamination from impacting semiconductor device yields and uniformity, they are not without problems. Therefore, other techniques/methods for reducing such contamination may be beneficial in semiconductor device manufacturing.
It will be appreciated that for simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.